As a substrate to fabricate a semiconductor integrated circuit, a silicon wafer fabricated by a CZ (Czochralski) method is mainly used. In each of recent advanced memory devices, a NAND flash memory having a three dimensional structure which has a process of laminating a multilayer film on a silicon wafer to increase a capacity and reduce a bit cost is used. A relatively initial stage of the process has a step of laminating tens of pairs of “SiO2+SiN” films. After the lamination, there are many three-dimensional complicated steps, e.g., a hole etching step of colmunarly etching members including a substrate, a step of forming a film of polysilicon on a sidewall, a step of etching SiN, and an electrode forming step, and performing each step in a state where the wafer largely warps can cause a failure.
Claim 8 in Patent Literature 1 has a description that a thin film is formed on one main surface of a substrate in a state where the substrate is warped in an opposite direction. However, according to the prior art, etching is performed for warping. In control over a warp amount provided by the etching, an etching rate must be fixed in a concentric shape, and forming a concentric warp shape which cancels out a warp provided by film formation is difficult.
Further, Patent Literature 2 has a description that a warp of an epitaxial wafer is identified in advance, a direction of a warp of a substrate is aligned to a direction opposite to a direction of a warp change which occurs in epitaxial wafer growth, and an absolute value of a warp of the epitaxial silicon wafer is reduced. According to the prior art, an object is to reduce a warp caused due to a lattice mismatch by selecting a concave or convex shape of a silicon wafer which is used for the substrate, but reducing a warp amount (Warp) whose size is hundreds of μm is difficult.